Communication  switching  apparatus for  switching data in multiple  protocol  data frame formats

ABSTRACT

An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/838,198 filed on Aug. 13, 2007.

FIELD OF THE INVENTION

The present invention relates generally to the field of serialtelecommunication and computing protocols, and more specifically totelecommunication and computing systems that utilize an enhancedcommunication protocol supporting a shortened frame size for moreefficiently communicating data payloads among selected devices within aconstrained neighborhood based on a unique ID within that neighborhood.

BACKGROUND OF THE INVENTION

A computing/communication network is generally understood to be aninterconnected or interrelated group or system of computers,peripherals, terminals, servers, switches, routers and other hardwareand software based devices connected by electrical, optical or wirelesstransmission media to enable the transmission and reception ofcommunications. Traditionally, telecommunication networks thatcommunicate voice, video and data over large distances were consideredto be categorically different than computer or data networks thatprimarily communicate digital data, typically over shorter distances.This distinction is now disappearing and emerging networking conceptsand technologies are causing a convergence of voice, video, data andwireless onto, for instance, a single, multiservice network paradigmbased on Internet Protocol (IP) standards. Conventionally, informationtransfer in networks follows a communication protocol that prescribeshow digital information is encapsulated for transmission betweenend-nodes in a network system. One popular network protocol is theEthernet™ protocol.

The Ethernet protocol as defined by various standards, including theIEEE std. 802.3, published Mar. 8, 2002 is currently considered to bethe dominant data networking technology. The Ethernet protocol is widelyaccepted as a means to communicate network packets to and fromedge-devices (or end-stations) over a wider array of networks rangingfrom LANS to wireless networks. Ethernet has retained its viability as acommunications technology even in the face of an explosive growth indemand for bandwidth and high data rate communications by evolving tomeet extant network performance standards. While the original wirespeedsfor Ethernet standards were only 10 megabits per second (Mbps), currentrates are upwards of 40 gigabits per second (Gbps) with rates of 100Gbps soon to be available. Ethernet® is a registered trademark of XeroxCorporation.

The Ethernet standard uses a packet (or frame) as a basic unit of datato communicate information over electrical, optical or wirelesscommunications media to devices connected to the network. The Ethernetprotocol specifies the rules (or standards) for constructing suchpackets or frames and this standardization has been one of the primarycontributors to the success of the Ethernet protocol as a networkingtechnology. The rules define, among other things, the minimum andmaximum length of a packet and the information that must necessarily bepresent in each packet. A standard Ethernet packet is generally between64 and 1518 bytes in length and includes 46 to 1500 bytes of data, plusa mandatory 18 bytes of header plus FCS information. Each packet (orframe) is required to include a source address (SA) and a destinationaddress (DA) that uniquely identify the source and the recipient of thepacket. In this regard, each network node (alternatively end-node,device, end-station, or edge-device) is associated with a unique MediaAccess Control (MAC) address that is 48 bits long.

Typically, the network comprises several local area networks (LANs),each of which may communicate through an intermediate network device,such as a bridge, switch or router, with the other LANs that comprisethe network. The intermediate device does not originate traffic of itsown although it may terminate (i.e. drop) packets that do not conform tothe Ethernet standard (also known as “illegal packets”). Ethernet is aconnectionless, broadcast based protocol intended for use in a sharedmedium. The intermediate devices use a forwarding table as well as theaddress information in the header of an incoming packet to decide wherethe incoming packet should be forwarded to. Forwarding tables can bepermanently defined (static) or built by the intermediate device bylearning the MAC addresses of devices on the LAN links. In this respect,every Ethernet compliant packet includes a mandatory 6-byte destinationaddress (DA), a 6-byte source address (SA), two2-byte E-type and a 4byte FCS for a total of 20 bytes of packet overhead and 14 bytes ofheader overhead. A minimum Ethernet packet size of 64 bytes (notincluding the preamble) involves a header overhead of about (14/64)*100or 22 percent. The size of the header affects the available bandwidth.It also affects the speed with which the header can be processed.Moreover, the Ethernet protocol imposes a fundamental limit on theglobal address space due to the finite number of address bits permittedin a Ethernet packet. The global address space limitation constrains thenumber of nodes in the network that can be explicitly addressed. Othernodes in the network may be considered to belong to a local network thatis hierarchically below and extends from an explicitly addressed “root”node. The nodes in this local network may be addressed using logicaladdresses valid only in the local network. Computing and resolving suchlogical addresses imposes a computational overhead in addition to theheader processing burden. Clearly, high-speed, Ethernet basedcommunications in a local network may be problematic due to the latencyintroduced by header processing and bandwidth limits.

One of the approaches to address the aforementioned issues is theconcept of a virtual local area network (VLAN). As opposed to a LAN,which represents a physical network system comprised of a plurality ofnetwork devices and the physical interconnection between them, such asfor example, Ethernet™ or fiber optic links, a virtual local areanetwork (VLAN) is logical segmentation of a single physical network intomultiple networks. A virtual LAN (VLAN) is a collection of networknodes, perhaps on multiple physical LAN segments, that can communicateas if they were connected to the same physical LAN without the need torepetitively process the standard Ethernet header. A given set ofnetwork devices may logically belong to several VLANs each of which iscapable of Ethernet based packet communication if the VLAN segmentationis done pursuant to the Institute of Electrical and ElectronicsEngineering (IEEE) 802.1Q draft standard Following the IEEE 802.1Q draftstandard, the use of a Virtual LAN (VLAN) identification (ID) (VLAN ID)as prescribed in the Institute of Electrical and Electronics Engineering(IEEE) draft standard 802.1Q. VLANS are set up by inserting a tag,called a VLAN tag, into each Ethernet frame. The tagged frame carriesVLAN membership information. The VLAN tag is 2 bytes in length. The last12 bits of the tag is reserved for a VLAN identifier (VLAN ID). Taggingcan be based on the source or destination Media Access Control (MAC)address. Each intermediate device maintains a table of MAC addresses andtheir corresponding VLAN memberships. VLAN-unaware devices transmit andreceive normal MAC data frames, such as untagged data packets.VLAN-aware devices are capable of transmitting and receiving tagged datapackets. The VLAN-aware devices switch packets based on the VLAN ID. TheVLAN ID presents a smaller header processing overhead. This approachreduces the header processing overhead while a packet is being sent, butit does not change the overall length of the packets that must becommunicated across the network. As noted above, an additional 2 bytesin the form of a 802.1q VLAN Tag added, are added to the header. For aminimum Ethernet packet size of 64 bytes (not including the preamble),the VLAN ID based approach introduces a header overhead of (20/64)*100or about 31 percent.

It is well known that shorter packets dominate network traffic. In suchinstances, the information carried in the header is about the same asthe actual data payload resulting in a significant header processingrelated overhead. Such a situation may arise, for example, where thepackets represent small, periodic, distributed data transfers associatedwith cellular transmissions or Voice over Internet Protocol (VoIP)traffic. A prior art approach to improve the header overhead to dataratio is header compression. Header compression is typically used toreduce the header overhead when using protocols such as real timeprotocol (RTP), user datagram protocol (UDP) and Internet Protocol (IP)on slow and medium speed links such as, for example, an air link. Headercompression involves the minimization of the bandwidth for informationcarried in headers by taking advantage of the fact that some fields inthe headers of consecutive packets in a packet stream remain static orchange in a predefined way. Currently, there are proposals to reduce the40-byte RTP/UDP/IP header to 4-5 bytes for instance. An exemplary headercompression scheme is described in S. Casner and V. Jacobson,“Compressing IP/UDP/RTP Headers for Low-Speed Serial Links,” IETF RFC2508, the contents of which are hereby incorporated by reference. Theseheader compression methods have to compensate for packet loss due tolink errors and link latencies to prevent the de-compressor fromappending incorrect header information to an out of sequence packet.

One attempt to improve the VLAN tag header has been described in U.S.Pat. No. 6,975,627 to Parry et al. which discloses a modification of tagfields in Ethernet data packets that relies on the existence, in currentEthernet standards, of a requirement for a header that precedes a tagthat is used to denote a number identifying a virtual local areanetwork. The invention is based on the use of the VLAN tag header toconvey the selected or proprietary information where the VLANidentification field is modified by inserting in place of the VLAN tagheader a field of the same size including selected information. Theinserted field may include a first field indicating the presence of theVLAN identification field and a second field of selected information.The main purpose of the Perry invention is to modify a packet withselected information on the assumption that the egress port isproprietary, thus avoiding the difficulties of techniques that includeadding data before or after existing data fields in the Ethernetprotocol. Perry discloses the use of auto-negotiation to confirm thatdevices connected by a data link are compatible so as to ensure that thedata link between the devices which are to form a common logical entitymust be such that every packet intended for transmission by way of thelink has a VLAN tag header. Perry's scheme allows control information tobe passed between the units of the stack, or in general, different unitswithin a physical system, with no increase in bandwidth for taggedpackets. The stack is a plurality of devices, such as a multiplicity ofhubs or switches, coupled together so that from the point of view of theexternal network, the plurality of coupled or “stacked” devices acts asa single logical entity. Perry's scheme inherits the 42 bytes/packetframe processing overhead associated with 802.1q Ethernet as previouslydescribed.

One area where the issue of header overhead takes on special importanceis where Ethernet switching fabrics are utilized as backplane fabrics ina computing/communication system. US Publ. Appl. No. 20050091304, forexample, discloses a control system for a telecommunication portal thatincludes a modular chassis having an Ethernet backplane and a platformmanagement bus which houses at least one application module, at leastone functional module, and a portal executive. In this patentapplication, a 1000BaseT (Gigabit Ethernet) backplane provides apacket-switched network wherein each of the connected modules acts as anindividual node on a network in contrast to a conventional parallel busconnection such as a PCI bus. US Publ. Appl. No. 20060123021 discloses ahierarchical packaging arrangement for electronic equipment thatutilizes an Advanced Telecommunication Computing Architecture (ATCA®)arrangement of daughter boards in the for an Advanced Mezzanine Card(AMC™) that are interconnected with a hierarchical packet-basedinterconnection fabric such as Ethernet, RapidIO, PCI Express orInfiniband. RapidIO is a trademark of the RapidIO Trade Association. PCIExpress is a trademark of the PCI-SIG. InfiniBand is a trademark of theIBTA (InfiniBand Trade Association). In this arrangement, the AMCs ineach local cube are connected in a hierarchical configuration by afirst, lower speed interface such a Gigabit Ethernet for connectionswithin the local cube and by a second, higher speed interface such as 10G Ethernet for connections among cubes. AdvancedTCA and the AdvancedTCAlogo are registered trademarks of the PCI Industrial ComputersManufacturers Group. ATCA and the ATCA logo are trademarks of the PCIIndustrial Computers Manufacturers Group. Other names and brands may beclaimed as the property of others.

The problems of an Ethernet-switched backplane architectures in terms oflatency, flow control, congestion management and quality of service arewell known and described, for example, by Lee, “Computation andCommunication Systems Need Advanced Switching,” Embedded IntelSolutions, Winter 2005. Intel is a registered trademark of IntelCorporation or its subsidiaries in the United States and othercountries. These issues have generally discouraged the adoption ofserial I/O protocols for communications between processors and memorythat would typically be limited to the smaller physical dimensions of acircuit board or a computer or communication rack or cabinet havingmultiple cards/blades interconnected by a backplane. Instead, the trendhas been to increase the capacity of individual chips and the size ofeach of the server blades in order to accommodate more processors andmemory on a single chip or circuit board, thereby reducing the need forprocessor and memory interconnection over the backplane.

Another fundamental problem with Ethernet backplanes is that thestandard Ethernet frames are less efficient than other packet basedbackplane technologies because of excessive packet (or frame) overheadwhich requires additional backplane bandwidth. For a line card tosupport a rate above 1 Gbit/s, would require the provisioning of a10-Gbit/s Ethernet backplane link. In addition to the frame processingoverhead, standard Ethernet lacks effective mechanisms for flow control,congestion management, and high availability. Although Ethernet providesthree priority bits in the VLAN tag that can be used to provide suchmechanisms, there is no industry standard on how to use these bits.Ethernet has no class based flow control mechanism, and only supports anXON/XOFF mechanism in some applications. Since most prior art systemsutilize layer 2 Ethernet switching which does not have these QoS or HAfeatures, these prior art systems are unlikely candidates for solutionsthat would overcome the limitations of the Ethernet backplanes.

Another downside of using Ethernet as a backplane switching fabric forsilicon-to-silicon interconnect is the lack of an infrastructure tohandle congestion management. This aspect is described in RobertBrunner, Shashank Merchant, “Congestion Management Requirements andProposals—A TEM's View”, the contents of which are incorporated herebyin there entirety. The congestion may arise from, for example, anunavoidable rate mismatch between the blades and between multiplechassis. Unfortunately, unlike communications over a computer networkwhere some latency is tolerable, intra-device and inter-bladecommunications cannot tolerate packets being discarded in the switchingfabric.

While many of the above mentioned limitations could be overcome byemploying new mechanisms that utilize non-Ethernet components, such anapproach cannot avoid the penalty of losing the cost advantages gainedthrough Ethernet's economies of scale. An exemplary non-standardmechanism would entail appending data onto the beginning or end of anexisting packet's data field. Recall that standard Ethernet packets havea prescribed maximum length. Appending data to an Ethernet packet canresult in an illegal packet, i.e. one whose length exceeds the maximumpacket length. An illegal packet will likely be ignored or dropped byintermediate devices as the packet progresses thorough the network.

In view of the above, it would be advantageous to provide an enhancedEthernet protocol that could overcomes the shortcomings of the existingapproaches to improving header efficiency and, particularly, that couldimprove over the prior art Ethernet switching backplanes in the area ofheader overhead, link utilization, quality of service (QoS), highavailability (HA), and latency while being inherently secure fromout-of-the-system snooping.

SUMMARY OF THE INVENTION

The present invention is directed to an enhanced Ethernet communicationprotocol that can support a standard as well as a non-standard (i.e.shortened) Ethernet frame size for more efficiently communicating datapayloads among selected devices within a constrained neighborhood basedon a unique address for each device within that neighborhood. In oneembodiment, the enhanced Ethernet protocol utilizes a VLAN like taggedEthernet frame (in a manner similar to the IEEE 802.1Q standard) andeach edge node/device/card in a local network/constrained neighborhoodis assigned a VLAN-ID like identifier which uniquely identifies thatnode. Ethernet data packets associated with the particular edge-node areidentified and classified within the constrained neighborhood of thisVLAN like domain using this VLAN-ID like identifier and therefore can becommunicated by an Ethernet switch inside of the constrainedneighborhood of this VLAN like domain based on the VLAN-ID like UniqueID instead of the conventional source address (SA)/destination address(DA) information in the standard Ethernet protocol. In one embodiment,the VLAN, VLAN-ID and Ethernet data frames can conform to the IEEE802.1Q standard. In this way, the present invention renders the SA/DAfields redundant thereby allowing their use for carrying bits comprisingdata payloads. In this manner, the overhead efficiency of the packettransfer may be increased, the length of the packet may be decreased, ora combination of both while leaving intact the ability to utilizestandard Ethernet based packets and network constructs.

In one embodiment, a single enhanced Ethernet frame format in accordancewith the present invention may be utilized among end stations and/oredge-devices in a local network/constrained neighborhood. In anotherembodiment, the present invention makes use of the variable features toprovide a plurality of enhanced Ethernet frame formats. Each frameformat representing an optimal packet configuration for the parametersgoverning communications between a pair of edge-devices, for example. Inan exemplary embodiment of the present invention, these parameters maybe arrived at by the process of auto-negotiation. In another embodiment,the parameters may reflect the size of each flow between the twoedge-devices, the frequency of such a flow and even a QoS with which theflow is to be delivered.

In one embodiment, the present invention is implemented for an Ethernetswitching fabric backplane of a computer system in accordance with thepresent invention is implemented as a multi-card Advanced Mezzanine Card(AMC) computer system based on an advanced TCA packaging arrangementhaving at least one processor card, and, optionally, a graphicsprocessor card, a hard disk drive card and a memory card that are allinterfaced to a management card having a multi-port Ethernet switch. Allof the processor cards and the memory card are connected via a backplanewith the multi-port Ethernet switch on the management card as theinter-card Ethernet switched fabric for the computer system via bitstream protocol processor chips located on each card. In one embodiment,the computer system is housed in a 3×2 picoTCA complaint packagingarrangement with redundant power supplies and shelf managementfunctionality. In this embodiment, conventional microprocessor cards maybe utilized with a serial bit stream processor such as for example, abit stream protocol processor as described below, coupled on eachprocessor card to the north-side bridge chip to package all off-boardcommunications as high-speed Ethernet switched packets and a bit streamprotocol processor is also utilized on the extended memory card tointerface between a memory controller chip and the Ethernet fabric ofthe computer system.

In one embodiment, the inter-card Ethernet switched fabric isaccomplished through a 10 GigE Ethernet interface via a bit streamprotocol processor or other suitable processor adapted for serializedprotocol processing and interface logic separate from themicroprocessor/controller chip and a 10 G Ethernet interface. The bitstream protocol processor encapsulates the memory address and controlinformation like Read, Write, number of successive bytes etc, as anEthernet packet and the memory provisioned on the processor, decodes it,performs the action and encapsulates the result on to Ethernet, which isdecoded by the bit stream protocol processor.

In one embodiment, a 10 G connection can be established between theelements on a blade, board or card via the bit stream protocol processorand interface logic. In another embodiment, a plurality of blades areconfigured to permit Ethernet connectivity over a backplane and may becommunicatively coupled using a non-blocking, Ethernet based switchingfabric. In still another embodiment, a plurality of processors areconfigured to permit Ethernet connectivity with main memory located onseparate blades, boards or cards, or even in separate shelves or chassisover cabled connections and may be communicatively coupled using anon-blocking, Ethernet based switching fabric.

The above summary of the various embodiments of the invention is notintended to describe each illustrated embodiment or every implementationof the invention. The figures in the detailed description that followmore particularly exemplify these embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be more completely understood in consideration of thefollowing detailed description of various embodiments of the inventionin connection with the accompanying drawings, in which:

FIG. 1 depicts a block diagram of a computing system in which oneembodiment of the present invention is exemplified.

FIG. 2 depicts a functional block diagram of an exemplary architectureof a bridging chip located on a single circuit board configured as aprocessor card in accordance with one embodiment of the presentinvention.

FIG. 3 illustrates a switched network and a MAC address based VLAN setupassociated with the switch S1 of the computer system of FIG. 1 of thepresent invention.

FIG. 4 depicts a VLAN tagged Ethernet frame compliant with IEEE 802.1Q.

FIG. 5 illustrates an exemplary Ether-short frame in accordance with oneembodiment of the present invention.

FIG. 6 depicts an exemplary header modification in the Ether-short frameof the embodiment of FIG. 5 of the present invention in which theexemplary EType is a Unique ID.

While the invention is amenable to various modifications and alternativeforms, specifics thereof have been shown by way of example in thedrawings and will be described in detail. It should be understood,however, that the intention is not to limit the invention to theparticular embodiments described. On the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The Ethernet protocol that is the subject of the present invention isdefined, for example, by IEEE Standard 802.3, published Mar. 8, 2002,although other Ethernet protocols presently known or to be adopted thatconform to other industry standards are also included within the scopeof the present invention. It will also be appreciated that the Ethernetprotocol is presented for ease of description and by way of exemplifyingthe various embodiments of the present invention but not by way oflimitation. Other protocols may be used within the scope of the presentinvention and the invention is not limited by the particular protocolemployed. In unrelated embodiments, the present invention admitsseparate protocols within each constrained neighborhood (or portionsthereof) of the system.

FIG. 1 depicts a computer system 10 in accordance with one embodiment ofa local network/constrained neighborhood of the present invention thatis implemented as a multi-card Advanced Mezzanine Card (AMC) computersystem based on an advanced TCA packaging arrangement having at leastone processor card 15, and, optionally, a graphics processor card 20, ahard disk drive card 25 and an extended memory card 30 that are allinterfaced to a manager card 35 having a multi-port Ethernet switch 40.All of the processor cards and the memory card are connected via abackplane 45 with the multi-port Ethernet switch 40 on the managementcard 35 as the inter-card Ethernet switched fabric for the computersystem via at least one processor chip located on each card, wherein theprocessor chip is adapted to process serialized protocols, such as forexample, a bit stream protocol processor chip 50 located on each card ofthe exemplary embodiment of FIG. 1.

In another embodiment, the computer system 10 is housed in a 3×2MicroTCA™ based packaging arrangement with redundant power supplies 55and shelf management functionality 60 for each 3-wide MicroTCA™ shelfthat can implement a picoTCA packaging arrangement. In this embodiment,conventional microprocessor MicroTCA cards 65 may be utilized with a bitstream protocol processor chip 50 coupled on each processor card 65 tothe north-side bridge chipset 68 via for example, a front-side bus 70,to package all off-board communications as high-speed Ethernet switchedpackets and a bit stream protocol processor chip 50 is also utilized onthe extended memory card 30 to interface between a memory controllerchip 75 and the Ethernet fabric 45 of the computer system.

In the exemplary embodiment of the present invention described above,and as illustrated in FIG. 1, the computer system includes a pluralityof cards, such as for example, the MicroTCA cards 65, that aredimensioned to conform to an industry standard and configured to bereceived in an enclosure whose dimensions and operability are alsoprescribed by the same or an alternative industry standard, such as forexample, the MicroTCA™ based packaging arrangement. The cards andenclosure cooperatively constitute the computing/communicationprocessing system of the present invention. The industry standard may becompatible with the MicroTCA standard, as set forth above, or the ATCAstandard well known in the art. The enclosure is configured to receive aplurality of cards, although in a specific embodiment, the functionalityof all or a portion of the cards may be presented on a single card, suchas for example, in a single board computer or other single card baseddevices without digressing from the present invention. As illustrated inFIG. 1, in these exemplary embodiments, each card may be differentiatedin terms of the functionality it is configured for. For example, thecard may be a memory card, a processor card, a storage area networkcard, a secondary processor card, a server card, a secondary fabric cardand so forth. Additionally, the enclosure may accept modules such as thefan modules 67 that are not based on the AMC™ or other industrystandard. In particular embodiments, each card may be provided with atleast one processor chip located on the card, wherein the processor chipis adapted to process serialized protocols, such as for example, a bitstream protocol processor chip 50 located on each card of the exemplaryembodiment of FIG. 1.

In the embodiment illustrated in block diagram form in FIG. 2, a bitstream protocol processor interconnects communications, both memory andI/O, via the Ethernet switched fabric backplane 45 at Ethernet linespeeds (alternately “wire speeds”)

It will be appreciated that the architecture illustrated in FIG. 1 ispresented by way of exemplification and not limitation. Thus theMicroTCA™ based architecture of FIG. 1 may be replaced by a typicalPersonal Computer (PC), well known in the art, within the scope of thepresent invention. The PC architecture may feature a single circuitboard, referred to as a motherboard, that includes a microprocessorwhich acts as the central processing unit (CPU), a system memory and alocal or system bus that provides the interconnection between the CPUand the system memory and I/O ports that are typically defined byconnectors along an edge of the motherboard. A Northbridge/Southbridgechipset serves as the interface between the CPU, the system memory andthe I/O ports. In an exemplary embodiment, the single circuit board ofthe PC based architecture may be used as the management controller hubcard 35 of the MicroTCA™ based architecture illustrated in FIG. 1 byaugmenting it with a bridge chip as illustrated in FIG. 2 and describednext.

Referring now to FIG. 2, there is illustrated an embodiment of a singlecard, exemplified in the specific embodiment as an AMC™ card adapted foruse in the MicroTCA™ based enclosure and architecture shown in FIG. 1 oralternatively as the motherboard of the PC architecture described above.In this alternate embodiment, the CPU (not shown) is operably coupled tothe first type of serial data transmission interface using the frontside bus 70. In a general embodiment illustrated in FIG. 2, the frontside bus (FSB) 70 of a conventional prior art chip, such as the Intel®Pentium 4 microprocessor, for example, the FSB 70 and the systemcontroller 68 (i.e. the Northbridge chipset, for instance) is interfacedto the bridge chip 50 that provides a two-way bridging function betweenthe first and second data transmission protocols. Intel and Pentium areregistered trademarks of Intel Corporation. In another embodiment, anASIC (not illustrated) replaces the Northbridge chipset or cooperateswith the Northbridge chipset. The ASIC is configured to interface withthe FSB 70 to create an Ether bridge that translates memory requests toencapsulated Ethernet packets. The ASIC in turn communicates with thebit stream protocol processor 50 of this embodiment.

For a more detailed description of the embodiments of FIG. 1 that areused to describe one aspect of the present invention, reference is madeto the previously-identified utility patent application entitled“TELECOMMUNICATION AND COMPUTING PLATFORMS WITH SERIAL PACKET SWITCHEDINTEGRATED MEMORY ACCESS TECHNOLOG,” Ser. No. 11/828,329, filed Jul. 25,2007, and the disclosure of which is hereby incorporated by reference.It will be understood, however, that the Ethernet protocol in accordancewith the present invention is applicable to numerous embodiments ofphysical components capable of implementing serial communication inaccordance with the Ethernet protocol within a constrained network asdefined herein.

In order to more clearly understand the present invention, an exemplarycommunication between a subset of cards of the computer system of FIG. 1will now be described. In this embodiment, a first processor card 15communicates with the extended memory card 30, the graphics processorcard 20 and the HDD card 25 over the backplane 45 via the intermediationof the multi-port Ethernet switch 40 located on manager card 35 Asillustrated in FIG. 1, a bridging chip 50 capable of transformingbetween communication protocols is disposed on the first processor card15 and serves as a communication interface between said first processorcard 15 and the other cards (and optionally modules) of system 10through the intermediation of the a multi-port switch 40 located onmanager card 35. In a general embodiment of the present invention asillustrated in FIG. 1, each card 65 is configured with a bridging chip50 capable of transforming between communication protocols to serve as acommunication interface between the card in question and the other cards(and optionally modules) of system 10 through the intermediation of themulti-port switch 40 located on manager card 35. In the specificembodiment discussed in relation with the illustration of FIG. 1, thebridging chip 50 is a bit stream processor based bridge chip 50 thatinterfaces the first processor card 15 to the switch 40 co-located withthe management controller hub on the management controller hub card 35(alternatively “manager card”). The extended memory card 30 and thegraphics processor card 20 are each interfaced to the switch 40 by aseparate corresponding bit stream processor based bridge chip 50 on eachcard. FIG. 1 illustrates the specific interconnects between the bitstream processor based bridge chips 50, the cards 15, 30, 20, 25 and theswitch 40.

In another embodiment of the present invention, the system 10 may beconfigured to operate using a first serial communication protocol andone or more cards 15, 30, 20, and 25, may be configured to operate usingone or more serial communication protocols native to the particular cardbut different than the first serial communication protocol. In thisunrelated embodiment, each of the cards 15, 30, 20 and 25 may be adaptedto use one or more bridge chips 50 that translate between the firstserial communication protocol and the serial communication protocolsnatively used on the particular card with which the bridge chip 50 isassociated. In an exemplary embodiment of the present invention, theswitch 40 may be based on a bit-stream processor architecture as willbecome clear from the description that follows. Once again, it should beemphasized that the bit stream processor architecture is presented byway of exemplification of the bridging chip and switch chiparchitectures but not by way of limitation. In other embodiments, anybridging chip or switch chip may be utilized within the scope of thepresent invention.

Referring now to the illustration of FIG. 3, there is illustrated inblock diagram form an exemplary architecture of the switch S showing theports 1-4 at which respective cards 15, 30, 20 and 25 are connected tothe switch 40 via the Ethernet switched backplane 45. As can be seenfrom FIG. 3, unlike a conventional network where there would only be oneEthernet address for the entire computer system represented by FIG. 3,in accordance with the present invention each of the respective cards15, 30, 20 and 25 (alternatively designated as A1, B1, A2, B2respectively) and switch 40 (alternatively designated S) are eachprovided with a unique MAC address such that each may be addressedindividually. It will be appreciated that the particular configurationof interconnections is exemplary and other configurations may be usedwithin the scope of the present invention. Each interconnect maytransmit or receive a serial data stream of packetized Ethernet databeing transferred to and from the switching chip 40 and the respectivecard. It will be appreciated that each of such interconnects may beconsidered to be a segment of a physical local area network LAN (L1)that includes the switching chip 40. The Ethernet protocol is used byway of example but is not intended to limit the scope of the presentinvention.

In one embodiment, the switch 40 is a VLAN-aware switch capable ofswitching a data packet or frame based on tag information. An exemplaryswitch 40 of the present invention may be a Fujitsu CX-4 based, 12-port10 Gbps Ethernet switch on a chip or the XG1200 and the XG700 switchesLayer 2, non-blocking, 10 Gb family of Ethernet switches powered byFujitsu's12-port 10 Gb Ethernet switch chip. It will be appreciated thatswitch 40 may be equipped with additional ports to allow the switch toconnect with one or more switches 42 (alternatively S2) and 44(alternately S3) (which may be resident within the system 10 or in othersystems outside the system 10—switches 42 and 44 are not illustrated)directly or through the switching fabric 45 illustrated in FIG. 1.Fujitsu and the Fujitsu logo are registered trademarks of FujitsuLimited.

One of skill in the art will appreciate that the aforementionedconfiguration is exemplary of the present invention in that severalother configurations are possible without departing from the scope ofthe present invention. In one embodiment, dual serial interconnects, onefor reception of data and the other for transmission of data, ensure acollision free domain. Alternatively, a single interconnect may be usedin place of a dual pair with appropriate signaling and synchronizationof the incoming and outgoing data streams may be utilized to preventcollisions using methods well known in the art.

In other embodiments, the computer system illustrated in FIG. 1 maycomprise one or more additional sets of circuit boards that communicatethrough one or more switches S2 to comprise additional LAN(s) (L2; notillustrated). Switches S1 and S2 may communicate over the backplane orthrough one or more intermediate devices in the extended networkexternal to the computer system of FIG. 1. Each of the LANs L1 and L2,as well as each of the subsystem members of that LAN, may be members ofa local network LN1 that define a constrained neighborhood forcommunications confined to that local network utilizing the enhancedEthernet protocol in accordance with the present invention.

In the illustrated embodiment of the present invention in FIG. 1, eachend-station (classically a computing system comprised of CPU, memory andI/O) or edge-device (an individually addressable subcomponent of aclassical computing system, such as any of cards A1, B1, A2, B2 or S) isglobally identified in the local and extended network by a MAC (MediaAccess Control) address as well as by a local logical address (the VLANID) which uniquely identifies the edge-device within the local networkLN1 as will be described in the following paragraphs.

In one embodiment, the constrained neighborhood for purposes of thepresent invention is the local network within which there is a mechanismprovided for allocating unique identification values in the form of aVLAN ID to each end-station and/or edge-device within the local network.In one embodiment, the local network includes an out-of-bandcommunication path separate for the Ethernet switching fabric by whichthe unique identification values are set and/or communicated. In anotherembodiment, an in-band communication message passing communicationscheme is utilized to convey information regarding the uniqueidentification to other end-station

According to one embodiment of the present invention, the edge-devicesin the local network LN1 communicate with edge-devices within the localnetwork LN1 using a first data frame format and with devices on theexternal network using the IEEE standard 802.3 frame format. The firstdata frame format is based upon a modification of the Institute ofElectrical and Electronics Engineering (IEEE) draft standard, 802.1Q. Adata frame configured according to the first data frame format containsinformation that associates the data frame with a virtual local areanetwork (VLANs) as defined in the Institute of Electrical andElectronics Engineering (IEEE) draft standard, 802.1Q. Accordingly, theedge-devices of the local networks L1, L2 of the computer system 10 ofthe present invention are grouped into one or more mutually exclusiveVLANs. The edge-devices within a VLAN communicate only with the othermember edge-devices in the VLAN whether located on the same or separatephysical LANs. VLAN membership (or a VLAN domain) can be defined byassigning specific ports on a switch to a particular VLAN or byassigning MAC addresses of specified edge-devices to the particularVLAN. In the later case, the end-device can be relocated on the networkwithout affecting its VLAN membership. In one embodiment of the presentinvention, each node in a VLAN is assigned a unique identificationdenominated the VLAN-ID. Once an edge-device is assigned a VLAN-ID, datapackets associated with the particular edge-node are identified andclassified within the environment of the VLAN using this VLAN-ID.

Referring now to FIGS. 3 and 4, there is illustrated a network switchand a MAC address based VLAN setup associated with the switch S of thecomputer system of FIG. 1 of the present invention. FIG. 4 depicts aVLAN tagged Ethernet frame that conforms to the IEEE 802.1Q standard.The Ethernet frame format begins with a 6-byte destination MAC addressfield followed by a 6 byte source MAC address field. A two-byte Ethernettype (ETYPE) field follows the source MAC address field. The ETYPE field(Ethernet Type value 802.1Qtag Type) identifies a frame as a TaggedFrame. There may be two ETYPE fields. The Etype field is followed by atwo-byte Tag Control Information (TCI) field. The two-byte TCI fieldcomprises a three-bit user priority field, one bit Canonical FormatIndicator (CFI) and a 12 bit VLAN Identifier (VLAN-ID) field. The 12-bitVLAN ID uniquely identifies the VLAN to which the frame belongs. A VLANtagged frame is a tagged frame where the Tag Header comprises a VLAN-IDvalue other than the null VLAN ID. The VLAN-ID field may be followed bya repeating pattern of the ETYPE and the TCI fields to allow nestedVLAN-IDs that allow nested VLAN implementations. The data or payloadfield follows the E-Type and TCI fields to complete the Ethernet frame.

Still referring to FIG. 3, the main purpose of the switch S is to relayframes between LAN segments as shown. The switch S accomplishes this byclassifying the frame as belonging to one and only one VLAN and usingthe VLAN-ID to switch the frame to the destination node or edge-device.In this regard, each switch S generally includes a global VLAN table aMAC learning table as shown in FIG. 3. In the primary embodiment of thepresent invention, each bridge chip 40 maintains a tag informationtable. The tag information table maps each available device/module inthe network to a VLAN ID or Unique ID. FIG. 2 is a block diagramillustration of the functional units of the bit stream protocolprocessor based bridge chip 50 of the present invention. As shown inFIG. 2, each bridge chip 50 maintains a tag information table that, in ageneral embodiment of the present invention, contains up to 4094 taginfo entries. Each entry maps device resource to a unique VLAN ID asillustrated in Table 1 below:

TABLE 1 Device/Resource Unique VLAN ID MEMORY-DIMM-1 (A2) VLAN-ID-1MEMORY-DIMM-2 (A2-2) VLAN-ID-2 I/O 1 (B1) VLAN-ID-3 I/O 2 (B1-2)VLAN-ID-4 . . . . . .

Table 1 illustrates the first step in the manual creation of a VLANtable of the present invention.

In one embodiment, each VLAN-ID from Table 1 is associated with a portnumber of switch 40 to generate a VLAN table shown as Table 2 below.

VLAN ID Port Number VLAN-ID-1 1 VLAN-ID-2 2 . . . . . .

Table 2 illustrates the second step in the manual creation of a VLANtable for each switch S1

In one embodiment, Table 2 may be created manually and loaded onto eachswitch S at system startup. In another embodiment, each edge-device isautomatically assigned a device VLAN-ID using a method such as theauto-negotiation protocol described in a following section. It willbecome evident to one of skill in the art that the present inventiondispenses with the need for reading (learning) an address as performedin a normal Ethernet switch using the MAC-address/VLAN-tag data pairbecause the data frame that traverses the switch will always be taggedwith a unique VLAN-ID that is either manually loaded or automaticallyassigned as noted above. In effect, packet flooding associated with thelearning mode in standard Ethernet.

One of the features of the present invention is the capability tointegrate a wide variety of functional modules (or end-stations) intothe computer system of FIG. 1 without the bandwidth, latency andscalability issues commonly associated with prior art parallel bus basedarchitectures. It must be appreciated that there is the possibility ofdissimilar technologies interfering with each other. One embodiment ofthe present invention provides a auto-negotiation protocol whereby thebridging chips 50 and optionally the switch chip 40, each of which maybe configured according to the bit stream protocol processorarchitecture in an exemplary embodiment of the present inventionassociated with edge-devices that are expected to engage in acommunications transfer during operation of the system 10, arbitrate theparameters that will govern the transfer.

Referring again to FIG. 2, the bit stream protocol processor basedbridge chip 40 (alternatively designated as X or Y when dissimilar frombridge chip 40) is equipped with a Resource Manager/Unique ID negotiatorwhich provides the auto-negotiation function. The parameters that may beestablished by the process of auto-negotiation include, for example, thedata rate, the payload, the Unique ID, and maximum frame size. In aparticular embodiment, the device Unique ID is assigned through theauto-negotiation process instead of being manually assigned as discussedabove. The Unique ID may be negotiated according to the data andinstruction processing functions being performed at each edge-device.This can allow the Unique ID to be used to represent a signal to theedge-devices to initiate certain predefined operations. Theauto-negotiation process may be based on IEEE Standard 802.3 publishedin 1998 or any other standard or method without digressing from thescope of the present invention. For instance, where Ethernet is theselected communication protocol, the Ethernet transceiver may include aphysical coding sublayer module which implements the Physical CodingSublayer (PCS) of the Ethernet protocol stack. The PCS functionalityincludes: Transmit, Synchronization, Receive and Auto-Negotiation.

In one embodiment, the bit stream processor may programmably fix thecharacteristics of the data frames that will be exchanged between a pairof edge-devices. In this respect, the data frame format exchangedbetween a pair of edge-devices over a VLAN will be substantiallyoptimized to suit the nature of the communication exchanged rather thanthe one-size-fits all approach of the prior art. Any information in thestandard header that is redundant or not useful within thelocal/constrained neighborhood may potentially be used to carry payloadrelated or other information thereby deviating from the standardprotocol. For example, the VLAN tagged Ethernet frame that conforms tothe IEEE 802.1Q standard may be modified so that the packet size is 20bytes with 8 bytes of header and 12 bytes of data. Such a modifiedpacket would be an illegal packet in standards based networks and wouldbe dropped (“runt” packets). However, internal to the constrainedneighborhood/local network, the Ether-short frame, although it violatesthe Ethernet standard in that it has a corrupt header (i.e. the SA andDA fields), variable length packets (due to auto-negotiation), and othernon-standard features, is recognized as a valid packet for communicationexchange between a pair of edge devices due to the auto-negotiationprocess whereby valid communication parameters are negotiated by and forcommunication between a pair of edge devices connected by acommunication link within the constrained neighborhood. In otherunrelated embodiments, multiple messages between edge devices may beconcatenated to realize a larger, standard-compliant packet, a 64 byteEthernet packet for example, which would be a valid packet both, withinthe constrained neighborhood as well as outside the constrainedneighborhood in the network at large where only standards compliantpackets are viable.

It will be appreciated that a plurality of frame formats are possiblewithin the scope of the present invention. Each frame format may bebased on the replacement of the IEEE 802.1Q specified VLAN-ID field bythe Unique ID of the edge-device obtained in the manner described in theprevious paragraphs. For example, a memory request by the CPU onprocessor 1 card (A1) that cannot be satisfied by the cache or otherlocal memory may be directed to the extended memory located on theextended memory card (B1). The memory request will traverse the FSB andappear as a signal at the FSB interface of the bridge chip X as shown inFIG. 2. One of skill in the art will readily recognize that the FSBsignal includes an address portion, a control portion and a dataportion. The Packet/Tag information Table module receives the addressportion. This module is provided with a programmable function thatallows the module to process the address portion and determine theUnique ID associated with the extended memory card B1.

In one embodiment, the programmability of the function may be supportedthrough the out-of-band SAC feature controlled by the SAC controllerco-located with the Resource Manager/Unique ID negotiator module. Theencapsulation engine receives the data and control portions directlyfrom the FSB interface of the bridge chip and the Unique-ID from thePacket/Tag information table module. The encapsulation engine assemblesthe bits in each of the data portion, the control portion and the UniqueID so that their relative positions reflect one of a plurality ofEther-short frame formats in accordance with the present invention asillustrated in FIGS. 5, 6, 8, 9 and 10, for example. It will beappreciated that one or more Ether-short frames may be generated toencapsulate the information in the signal received from the FSB. EachEther lite frame may have a single format selected from a plurality ofavailable formats.

In one embodiment, the selection of a particular Ether-short frameformat is programmably controlled via the SAC feature controlled by theSAC controller co-located with the Resource Manager/Unique ID negotiatormodule. The output of the encapsulation engine is received at one of theparallel serial translator modules downstream of the encapsulationengine. The parallel serial translator serialazes and packets andtransfers them over the backplane to the switch S. The switch S switchesthe packet based only upon the Unique ID as described in a precedingparagraph. The packets are received at the bit stream protocol processorbased bridge chip Y on the extended memory card B1. The bridge chip B1is selected to bridge between the Ether-short frame format and theprotocol native to the extended memory B1.

In an exemplary embodiment, the extended memory B1 may communicate usingthe SPI 4.2, PCI-Express and other protocols well known to the artwithin the scope of the present invention. One or more Ether-short dataframes representing the response of the extended memory B1 to the memoryrequest are received at the ingress side of bridge chip X. Aparallel/serial translator at the ingress parallelizes the Ether-shortframe and forwards it for receipt at the decapsulation engine. Thedecapsulaton engine recognizes the Ether-short frame format,disassembles it into the appropriate data and control portionsrecognizable by the FSB and forwards it to the Packet/Tag Informationmodule. The Packet/Tag Information module strips the Unique-ID in theincoming Ether-short frame, matches it to an address and generates theappropriate address portion which together with the data and controlportions output by the decapsulation engine, comprise a response signalappropriate for transfer over the FSB to the processor on the processor1 card. The illustrated embodiment of the bridge chip is equipped withscheduling, queuing, and traffic director modules that modulate theoutput of the encapsulation engine and the input to the decapsulatonengine to implement QoS and other features absent in the standardEthernet protocol. It will be apparent to one of skill in the art thatthe particular operations described here are exemplary of the process ofbridging between two message transfer formats. Other processes may beused within the scope of the present invention.

One of the features of the present invention is that every packettraversing the switch S utilizing an Ether-short format has a Unique IDthat alone is used to switch the packet at the switch S within theconstrained neighborhood (i.e. the localized or contained network). Thisrenders redundant all other fields of the packet except the FCS field.In particular, both the destination address (DA) field and the sourceaddress (SA) field of the conventional Ethernet protocol are renderedredundant. Transmitting a frame with redundant data increases the frameprocessing overhead and leads to the inefficiencies that have generallyprevented the adoption of the Ethernet protocol for communications amongsub-components of a conventional computing system. In contrast, theenhanced Ethernet protocol of the present invention makes these fieldsavailable for data payloads such that the overhead efficiency of thepacket transfer may be increased, the length of the packet may bedecreased, or a combination of both may occur. It must be appreciatedthat the computer system of the present invention still retains thecapability to communicate using standard Ethernet if the network nodesthat want to communicate cannot negotiate the Unique ID as acommunication parameter as will be explained below.

In one embodiment, a single Ether-short frame format in accordance withthe present invention may be utilized among end stations and/oredge-devices in a local network/constrained neighborhood. In anotherembodiment, the present invention makes use of the variable features toprovide a plurality of Ether-short frame formats. Each frame formatrepresenting an optimal packet configuration for the parametersgoverning communications between a pair of edge-devices, for example. Inan exemplary embodiment of the present invention, these parameters maybe arrived at by the process of auto-negotiation. In another embodiment,the parameters may reflect the size of each flow between the twoedge-devices, the frequency of such a flow and even a QoS with which theflow is to be delivered.

In one embodiment of the present invention, the encapsulation engineorders the bits in the Ether frame so that the DA field places the first48 bits of data, the SA field places the following 16 bits of data.Since the computer appliance 10 may be connected to an external network,the edge-devices of the present invention may exchange information withone or more external edge-devices/end stations. This exchange isconducted using standard Ethernet packets necessitating the preservationof header information in a packet traversing the external network. Toavoid the header processing overhead, the header information may becompressed into 4 bytes using the header compression method described inU.S. Pat. No. 6,804,238, the contents of which are incorporated hereinby reference. The four-byte header is placed after the SA field. Thisinformation is used to regenerate the full header for packetstransmitted to the external network. The header may also be used tosupport the process of segmentation and assembly as will be described inthe following paragraph.

FIG. 6 illustrates another embodiment of the present invention, whereinthe frame includes a defined header of 32 bits The 32-bit headerincludes start-of-packet (SOP), end-of-packet (EOF) information thatfacilitates packet delineation. To accommodate a switched environmentwith CoS/QoS, a 12-bit source Unique-ID and an eight-bit sequence numbermay be included in the header field to help identify segments belongingto the same packet. The E-Tag and the Unique-ID follow the header field.Regardless of the data placement described above, the Ether-short framecould be a “double-tagged” VLAN frame capable of accepting a stackedVLAN-ID implementation if necessary. It will be readily evident to oneof skill in the art that the data frame format of the present inventionprovides a much improved header to data ratio in comparison to prior artapproaches.

It is generally more efficient to transmit a larger frame—so thatheader-to-data ratio is smaller and therefore better performanceresults. Queues build up in a switch when traffic from several inputsmay be heading for a single output. In general, once a packet isextracted from a queue and its transmittal initiated, the process willcontinue until the whole packet is transmitted. The longest time that aqueue output can be tied up is equal to the time it takes to transmit amaximum sized packet. Fixed length cells mean that a queue output isnever tied up for more than the time it takes to transmit one cell,which is almost certainly shorter than the maximally sized packet on avariable length packet network. Thus, if tight control over the latencyexperienced by cells when they pass through a queue is important, cellsrather than the standard Ethernet frame or packet are advantageous.

In one embodiment, the bit stream protocol based bridge chip utilizesthe process of auto-negotiation to fix the size of packets and a UniqueID characterizing communications between edge-devices in the computersystem. The resultant Ether-short frame is then formatted according tothe auto-negotiated parameters.

In an alternate embodiment of the present invention each Ether-shortframe may be further segmented into cells of a fixed size using thesegmentation function of the bit stream protocol processor based bridgechip. For example, a segmentation of an original 600 bytes Ether-shortdata frame to three fixed size cells may be performed wherein each cellcarries 256 bytes of data.

In situations where each data flow is very small, but the number of dataflows are large, the header-to-data ratio is very large and headerprocessing overhead can overwhelm the computer system of FIG. 1. Anexemplary situation is the use of voice packets that are very small withthe payload usually lying between 20 to 150 bytes with RTP/UDP/IP headerof 40 bytes (IP header=20 bytes, UDP header=8 bytes, RTP header=12bytes). In a fixed size Ether-short frame configured for carrying 2⁶bytes of data, a frame with a total size of 78 bytes will be needed totransmit the 20 bytes of IP voice data. The header overhead to dataratio will amount to 30 percent. This includes the 4 bytes of paddingoverhead to meet the fixed frame size. A standard Ethernet frame withVLAN Tag sized to carry 64 bytes/frame will result in a header overheadto data ratio of 37 percent. Clearly, the Ether-short frame inaccordance with this embodiment is more efficient because it can beprogrammatically altered.

The advantage of the fixed cell approach, according to one embodiment ofthe present invention, can be seen from the resources required totransmit 150 bytes of IP voice data. In this case, using the Ether-shortframe, would require the transmission of three equal length Ether-shortframes with the total header overhead/data ratio amounting to about 23percent. Clearly, the fixed cell approach of the present invention ispreferable over the standards driven variable packet sizes.

According to another embodiment of the present invention, theEther-short frame is recognized and remains viable only within theconfines of the constrained neighborhood/local network. At the time, orprior to transmitting the Ether-short data frame over a sharedcommunications medium external to the constrained neighborhood/localnetwork, the bit stream processor based bridge chip preferablyreconfigures the frame (packet) using the segmentation and reassemblyprocess by reinserting the Ethernet header including the SA and DAfields if needed. The reconfigured packet conforms to the Ethernetstandard extant the network external to the constrainedneighborhood/local network to enable the packet to be recognized andforwarded by the intermediate level devices on the network. However,internal to the constrained neighborhood/local network, the Ether-shortframe violates the Ethernet standard in that it has a corrupt header(i.e. the SA and DA fields), variable length packets (due toauto-negotiation), and other non-standard features. As such, the EtherLite frame is a technically “illegal” frame if viewed from outside ofthe constrained neighborhood/local network. External snooping agentsthat depend on recognizing the standards defined features of a framecannot decipher the frame. Even if a frame in accordance with theEther-short enhanced protocol were to egress beyond the constrainedneighborhood/local network and appear on the external common sharedmedium, the errant packet meets the criteria for various early discardconditions on intermediate devices including routers, switches, bridges,hubs or edge-devices. In effect, the packet is either dropped and/orprevented from being forwarded over the shared transmission mediumcontributing to an inherently secure computing/communication system forthe constrained neighborhood/local network.

In one embodiment, the bit stream protocol processor allows line speedQoS packet switching that is utilized to implement a simple token basedcommunication in Ethernet. The source address (SA) and destinationaddress (DA) and E-type like VLAN Tag is used for negotiating a uniquetoken between end points on a communication link. The E-type extensionsmay be, for example, Request for UNIQUE ID or TOKEN GRANT; datacommunication with the granted token and request to retire the TOKEN.Once the TOKEN has been granted, the SA and DA fields are used alongwith the E-type to pass short date. This may also be extended to includelarge blocks of data for STA, and SAS. In other embodiments, once aUNIQUE ID is negotiated between end-points and an intermediate nodeconnecting these end-points, a fixed frame size is used to endow thelink with predictable performance in transferring the fixed frame andconsequently meet various latency requirements. For example, the SA/DApair could be used to transmit 12 bytes of data, 2 E-Type bytes and 2bytes TAG, instead of the traditional 64 byte payload for a conventionalEthernet packet. In case the network nodes at the ends of acommunication link fail to negotiate a unique token between them, thestandard Ethernet packet protocol based communication is used betweenthese network nodes. Such a situation may occur where one of the nodesis external to the computer system and the packets have to traverse atleast a portion of the network outside the contained network. Thissituation may also arise within the contained network when one or bothnetwork nodes are incompatible to initiate and/or continue packet basedcommunications using the Unique ID of the present invention. It will beappreciated that the fixed frame may be expanded or contracted to aframe of any arbitrary size that is viable within the constrainedneighborhood and yet remain within the scope of the present invention.

In another embodiment, the same interface could provide a fixed 2K Blocksize frame for Disc—(data follows the E-Type and TAG). In this respect,the present invention enables a programmable frame size Ethernetconstruct as opposed to the variable frame size construct known to theart. This capability can be especially useful in iTDM type ofapplications because it enables packetizing TDM traffic within theframework of ATCA, for example.

One of the challenges preventing the prior extension of an Ethernetbased switching fabric beyond the current level of the NIC has been theexpected overhead associated with regenerating the spanning tree thatrepresents the dynamic understanding of the topology of neighboringEthernet connections. The increasing the number of MAC addresses thatneed to be assigned as a result of extending the edge of the Ethernetswitching fabric beyond the NIC level will result in a predictableincrease in the amount of time that is necessary to resolve the SpanningTree Protocol (STP) that is used to update all of the nodes in thenetwork and generate a set of neighboring Ethernet addresses when theyare any changes of computing equipment within the firewall of a givenorganizational entity, for example.

Embodiments of the present invention may provide for several approachesto addressing the issues associated with the overhead of solution of thespanning tree protocol as a result of populating a given organizationalnetwork with a larger number of MAC addresses that extend the Ethernetfabric to the card level with the computing architecture in accordancewith the present invention.

In one embodiment, MAC addresses could be assigned only at switch on MHCof a given box and an internal configuration could be used within thebox with a bit stream protocol processor provided on the network edge ofthe switch that would be responsible for further processing of packetsas they cross the box/network boundary. One internal configuration couldbe the use of an extended Ethernet addressing scheme within the box thatwould be adapted to better facilitate the transmission of shorterpayload packets among the components within that box. Another internalconfiguration provides each card with a plurality of switched Ethernetports, where some of those ports are effectively configured within theswitch on the MHC to be only capable of internal switching and other ofthe ports are adapted to send packets across the box/network boundary.In each of these embodiments, the bit stream protocol processors on eachcard and at the MHC switch are provided with additional intelligence andinformation to discriminate between internal packet communications andexternal packet communications and also to resolve the internaladdresses for packets received from outside the box.

Another embodiment would assign MAC addresses at the card level andwould rely on the increasing power of the processing of the spanningtree inside a given firewall boundary to address and an assumption thatchanges of MAC addresses within the firewall boundary will be no morefrequent than changes of MAC addresses outside the firewall boundarysuch that the overhead associated with the regeneration of the spanningtree would be within acceptable limits.

Another embodiment utilizes known characteristics of the picoTCA boxeswithin a firewall boundary that are available through the RAC/SAC, IMPIor MHC to produce a pre-simplified version of the solution to thespanning tree within that firewall boundary. Another approach is to usethe reduced STP approach as described in IEEE 802.1w.

Concurrency control is also used as part of the extended Ethernetprotocol. This could also “add” to the CPU wait cycles if more than oneprocessor requests the same block of memory. In a sense that would be acomponent of latency because the processor and the instructionsscheduled for execution cannot distinguish between data localitydependent latency (speed of access and transfer) versus concurrencycontrol based data access “gap” because barring data mirroringconcurrent access is not instantaneous access.

In one embodiment, latency and contention/concurrency issues within theEthernet switched fabric are resolved within a “constrained network”Deterministic latency (tolerable margin jitter) through a “wellcontained network” (such as the packaging arrangement as describedherein) is indeed possible. Switching priority, dedicated ports, such asa pseudo port to dedicated memory ports, communicating over Unique IDsbetween these ports are the methods to achieve this.

Finally, while the present invention has been described with referenceto certain embodiments, those skilled in the art should appreciate thatthey can readily use the disclosed conception and specific embodimentsas a basis for designing or modifying other structures for carrying outthe same purposes of the present invention without departing from thespirit and scope of the invention as defined by the appended claims.

1. A multiport network communication switch for providing datacommunication between devices coupled to the switch, comprising:plurality of port Interface for coupling to communicating devices to theswitch and, processing logic for receiving data from a port of theswitch in a first protocol data frame format configured for thereceiving port and, for transmitting data to another port of the switchin a second protocol data frame format configured for the transmittingport and, processing logic for identifying the transmitting port of theswitch from the received data in the first protocol data frame format,and processing logic for translating the first protocol data frameformat to the second protocol data frame format.
 2. The switch of claim1, comprising; an external programmable interface connected to theswitch for configuring the first protocol data frame format and thesecond protocol data format for each port of the switch.
 3. The switchof claim 2, comprising; at least a port interface for coupling to adevice for receiving and transmitting data in both of the first protocoldata frame format and the second protocol data frame format.
 4. Theswitch of claim 3, wherein; the first protocol data frame format is incompliance of the industry standard Ethernet protocol.
 5. The switch ofclaim 3, wherein; the first second protocol data frame format is incompliance of the industry standard protocol data frame format and, thesecond protocol data frame format is a non-compliant version of theindustry standard protocol data frame format.
 6. The switch of claim 5,wherein; the first protocol data frame format is in compliance of theindustry standard Ethernet protocol.
 7. A bridge device for receivingand transmitting data between two communicating devices coupled to thebridge, comprising: an interface port for coupling to a first device toreceive and transmit data in one of at least two different protocol dataframe formats and, a second interface port for coupling to a seconddevice to receive and transmit data in the other of the at least twodifferent protocol data frame formats and, processing logic to receiveand transmit data in one of the at least two different protocol dataframe format from the first device and, processing logic to receive andtransmit data in the other of the at least two different protocol dataframe format from the second device and, to translate the receivedprotocol data frame one of the at least two different protocol dataframe formats to the other of the at least two different protocol dataframe format.
 8. The bridge device of claim 7, wherein; the protocoldata frame format of the first device and, the protocol data frameformat of the second device are programmable by an external portconnected to the bridge device.
 9. The bridge device of claim 7,wherein; the protocol data frame format of the first device ispreconfigured and, the protocol data frame format of the second deviceis programmable by the first device.